1. Field of the Invention
The present invention relates in general to integrated circuit (IC) fabrication and testing processes and in particular to the use of a carrier for holding an array of IC dice during testing and other processing steps.
2. Description of Related Art
FIG. 1 illustrates a typical prior art process flow for fabricating, packaging and testing ICs having embedded repairable random access memories (RAMs). A RAM includes rows and columns of cells for storing data, and a laser-repairable RAM includes spare rows or columns that can be used to replace rows or columns containing defective cells. When an IC chip containing a laser-repairable memory has a defective row or column, a laser alters the IC chip by cutting selected fuses on the surface of the IC so that the IC uses a spare row or column in lieu of the defective row or column.
In the process flow depicted in FIG. 1, the ICs are initially fabricated as an array of IC dice on a semiconductor wafer (step 10). The laser-repairable memory embedded in each IC is then tested before the IC dice are separated from the wafer (step 12). Some ICs include built-in self-test (BIST) circuits which automatically test their embedded memories and generate data at pads on the surfaces of the dice indicating which cells are defective. In such case a wafer-level IC tester employed at step 12 probes pads on the dice to acquire the data the BIST circuits within the dice produce during the test and to provide power and ground to the dice during the memory test. The IC tester may also perform other tests at step 12 such as, for example, parametric tests in which the current drawn at the IC's power terminals are measured. A laser repair system then processes the memory test data for each IC to determine which of its embedded memory rows or columns contain defective cells, determines how to allocate spare rows and columns to repair the memory, and then employs a laser to repair any defective memories (step 14). After repairing the defective memories, the memories may be again tested while the dice are still at the wafer level to ensure that the repair was effective (step 16). The dice may also be subjected to additional logic or parametric testing at this point.
The wafer is then cut to separate (“singulate”) all of the dice (step 18), and the dice that pass the post-laser repair test at step 16 are installed in IC packages (step 20). The packaged ICs may then be subjected to additional screening tests (step 22), and the packaged ICs that pass those tests are then subjected to a burn-in process (step 24). The burn-in process applies thermal and electrical stresses to the ICs for a specified amount of time for the purpose of inducing marginally operable ICs having inherent defects to fail. Typically ICs are burn-in tested by placing them in circuit board sockets and then loading the circuit boards into a convection oven which elevates their temperature to stress them thermally. While the ICs are being heated, power supplies and test signal generators linked to their power and signal I/O terminals stress them electrically. After burn-in, the ICs undergo detailed final testing (step 26) including high frequency logic tests and other tests. During final testing the parts may be “binned” according to speed grade or other performance levels.
The process illustrated in FIG. 1 includes four separate testing steps 12, 16, 22 and 26. A wafer level tester carries out the tests at steps 12 and 16 before the dice are separated from one another and packaged so that only the dice that pass those tests are packaged. Some manufacturers merge the post laser memory testing step 16 into pre burn-in testing step 22 or eliminate pre burn-in testing step. But in doing so they encounter the added costs of packaging more defective dice or expending burn-in resources on dice that could have been classified as defective before they were subjected to burn-in. Since a wafer level IC tester must include a separate data input/output channel to communicate with each IC pad it accesses during a test, tests carried out at the wafer level are often limited to those requiring a tester to access only a relatively few pads on each IC. To carry out the tests at steps 22 and 24, the packaged ICs are typically installed in load boards that enable an IC tester to access all IC signal, power and ground pins of each packaged IC.
Die that are to be used, for example in flip-chip module (FCM) or hybrid modules are not separately packaged. In an FCM, a bare die is mounted directly on a substrate using solder balls, polymer balls, spring contacts or other means to conductively link pads on the IC dice to pads on the substrate. Some FCM manufacturers do not attempt to test dice after they have been singulated, but instead choose to test only the assembled FCM. However since a single defective dice renders the entire FCM defective, many manufacturers find it preferable to test singulated dice before they are incorporated into FCMs.
FIG. 2 is a process flow diagram illustrating a prior art process for producing known good dice to be installed in FCMs. After wafer fabrication, testing at the wafer level, and laser repair (step 28), and after the dice are singulated (step 30), a die pick machine picks up and places each IC that passes wafer level testing on a testing substrate (step 32) so that it may be subjected to pre burn-in testing (step 33). After the dice are subjected to burn-in (step 34), the die pick machine places dice on the testing substrate (step 35) so that it may be subjected to final testing (step 36. The known good dice are then installed in FCMs (step 37), and the FCMs are then tested (step 38).
This system ensures that only known good dice (KGD) are incorporated into FCMs and avoids the need for using individual carriers which can damage some of the dice and provides an interconnect system having impedance characteristics that can be much closer to that of the interconnect system that will later link the dice to the FCM substrate. However the need to separately handle each IC chip during the many processing steps occurring after singulation increases the cost and lowers the speed of the process.
FIG. 3 illustrates a “wafer-level” testing approach to providing KGD for incorporation into FCMs. After wafer fabrication, memory testing and laser repair (step 40), the dice are subjected to burn-in testing (step 41) and detailed final testing (step 42) while still in wafer form. The dice are then singulated (step 43) and the KGD are incorporated into FCMs (step 44) that are then tested (step 44). Note that in this process flow all processing and testing steps needed to identify the KGD are carried out at the wafer level before the dice are singulated.
This approach greatly reduces the number of processing steps because IC chips are not handled individually until the KGD are ready to be installed in the FCMs. However the system requires use of a general purpose wafer level IC tester at step 42 that can access all of the signal pads of all of the dice and conduct every type of test needed. Since the dice on a single wafer can collectively have a very large number of signal pads, it is usually not practical to provide a tester having a sufficient number of channels to access all of the signal pads concurrently. Therefore wafer level IC testers that carry out final high frequency functional and other tests on dice normally test only a limited number of the dice on a wafer concurrently. After a group of dice are tested, a chuck holding the wafer repositions the wafer so that the tester's probes can access pads of another group of dice to be tested.
One advantage of the wafer level process flow of FIG. 3 is that it does not require manipulation of individual dice until they are ready to be installed in FCMs. But the process flow of FIG. 3 has an inherent inefficiency not shared by the process flow of FIG. 2. In the process flow of FIG. 2, the memory and other pre-laser repair testing carried out at step 28 will often identify defective dice that cannot be laser repaired. Those dice are discarded after singulation at step 30 and are not further tested at step 33. Similarly dice that fail pre burn-in tests at step 33 can be discarded so that they do not needlessly consume burn-in resources at step 34 or final testing resources at step 36. The process flow of FIG. 3 may conduct analogous test and burn-in steps on the wafer level dice, but since the dice are not singulated until after all testing and burn-in steps are complete, it is not possible to discard dice found to be defective after each test. Thus all dice are subjected to all test and burn-in steps that may occurs even after some dice have been found to be defective. Such redundant testing of known defective dice is an inefficient use of test and burn-in resources and can be particularly problematic where dice yields are low.
What is needed is a die carrier permitting a process flow that makes efficient use of testing and burn-in resources while minimizing the amount of individual die manipulation, which does not damage the dice, and which can accurately position dice having closely spaced contacts with a high degree of accuracy despite any lack of uniformity in dice dimensions.